JUST over a month after first proposing a new framework to succeed Moore’s Law, Huawei’s semiconductor chief He Tingbo has released a significantly expanded second version of her landmark paper.

Published Friday on ChinaXiv, the V2 edition of the “Time-Scaling Theory for Multi-level Electronic Systems” — known as “Tao (τ) Law” — shifts from theoretical foundations to concrete engineering implementation and product roadmaps.

While V1 answered why the industry needs a new scaling model after Moore’s Law, V2 answers how to make it work. The core principle remains: Chip optimization is no longer about making transistors smaller, but about making signals travel faster. The theory centers on reducing the global “time constant” (τ) across transistors, circuits, and entire systems.

The new paper provides critical details on Huawei’s “Logic Folding” technology, introducing the “Gear Ratio” concept for 3D stacking. When this ratio approaches 1, chip stacking can shift from “macro-block optimization” to “cell-level continuous optimization” — a breakthrough that enables Logic Folding to outperform traditional 3D designs.

Crucially, V2 backs the theory with real production data. Comparing the upcoming Kirin 2026 against the current Kirin 9030 Pro on the same process node, the Logic Folding design delivers a 53% increase in effective transistor density (from 155 to 238 MTr/mm²), a 30% reduction in critical wiring length, and a 41% cut in power consumption thanks to lower operating voltage.

The paper outlines at least four future Kirin generations, all adopting Logic Folding. The Kirin 2026 and 2027 have completed tape-out, with CPU performance cores projected to break 4GHz by 2029 — achieved through architecture innovation rather than advanced lithography.

For AI chips, the Ascend series will continue with chiplet and 2.5D packaging through 2026, with Logic Folding expected to debut around 2030. The paper projects AI hardware integration could increase 100-fold by 2035.

V2 also explains how Tao Law scales from single chips to massive AI clusters. He notes that over 80% of system energy and 70% of costs in large AI systems go to data movement, not computation. Future optimization, she argues, must focus on shortening data transfer time between chips, servers, and racks.(SD News)